1. Field of the Art
The present invention relates to bit phase synchronizing circuitry advantageously applicable to a transmission system, switching system or similar high-speed data transmission system, and a PLL circuit therefor.
2. Description of the Background Art
Conventional bit phase synchronizing systems select one of multiphase clocks each having a particular phase which is determined to have an adequate relation to received data in relation to timing. In this type of system, a selector selects one of the multiphase clocks. Received data are input to a timing decision circuit. The timing decision circuit determines whether or not the timing of the clock selected and that of the input data are adequate. A selection controller generates a control signal based on the output of the decision circuit and controls the selector therewith. Such a procedure is repeated until bit phase synchronization has been set up.
However, the above conventional system has the following problems. Because the selector switches the clocks, conventional control over the selector causes noise to be superposed on the clocks. Such noise cannot be obviated without the selector control being more sophisticated and without arranging the selection controller and selector with extreme precision for timing adjustment. This kind of arrangement is not readily practicable.
A communication system using burst-mode transmission has recently been proposed in various forms. For example, Atsushi Iwamura et al. teach "A Bit Synchronization Circuit for Burst Signals for High-Speed PDS Systems", Technical Report, The Institute of Electronics, Information and Communication Engineers of Japan, September, 1995, SSE95-83, IN-95-54, and CS95-103. Specifically, a high speed clock whose rate is several times as high as a transmission rate is frequency-divided in order to generate multiphase clocks each having a particular phase. After the input of a reset signal, data are sampled on the basis of the multiphase clocks. Transition points are detected from the data sampled in the respective phase. Finally, the data sampled in the phase estimated to be stable is selected.
The problems with the above burst adaptive synchronization scheme are as follows. The clock whose rate is several times as high as the transmission rate naturally results in expensive high speed devices for constituting, e.g., an LSI (Large Scale Integrated circuit). Further, bit phase synchronizing circuitry has customarily been designed to be reset by a reset signal appearing at the boundary between burst cells, to set up synchronization based on the transition point of the subsequent burst cell, and to hold it until the next reset signal appears. It is therefore necessary to bring the clock frequency being used by the synchronizing circuity and the transmission rate into accurate coincidence, or to make the length of a burst cell short enough to obviate synchronization errors attributable to a difference in frequency. This cannot be done unless the synchronization with burst data which is more strict than synchronization with continuous data, is effected in an extremely short period.